The present invention generally relates to a timing circuit (control method) that can change a clock period depending on an input signal (control voltage), and more specifically, relates to a timing circuit (method) for controlling a refresh period of a DRAM depending on a temperature.
In DRAMs, data are charged in capacitors of cells as charges. Accordingly, the data (charges) will be lost as leakage current with a lapse of time. Therefore, the refresh operation is periodically required for rewriting (charging) the data (charges) of the cells.
In general, as the temperature increases, data of each cell of the DRAM is lost more quickly. Therefore, the period short enough to fully retain the data even at the maximum operating temperature of a chip including that DRAM is normally selected as a period of the refresh operation. As a result, the refresh is constantly carried out with such a selected short period regardless of the actual operation temperature of the chip, so that the power consumption for the refresh becomes large.
For example, the data retention characteristic of a DRAM is in general such that its data retention time becomes about twice longer every time the temperature of a chip drops by 10° C. Specifically, the refresh that is required per 15.6 ↑¼s at the maximum operating temperature of 70° C. may be carried out per about 500 ↑¼s, which is 32 (25) times longer, at a low temperature of 20° C. Accordingly, in many cases, at the low temperature, the refresh is performed at frequency more than 10 times an actually required period (frequency) during a data retention mode, resulting in more than 10 times consumption of useless power. Therefore, it is necessary to reduce the wasteful power consumption caused by the refresh at an ordinary temperature or a relatively low temperature.
For reducing the wasteful power consumption caused by the refresh, there is a method that obtains a refresh period depending on a temperature of a chip including a DRAM. FIG. 1 is a diagram showing conventional circuit examples for monitoring a chip temperature and obtaining a refresh period of a DRAM depending on the monitored temperature. In FIG. 1, (A) is a block diagram of a circuit comprising a ring oscillator 1 having multi-stage inverters, an operational amplifier 3 and a buffer, wherein an oscillation period of the ring oscillator 1 is buffered and a buffered output (TDT) 2 is used as a temperature dependent timing for determining a refresh period. In the circuit shown at (A) in FIG. 1, the operational amplifier 3 compares a constant reference voltage VR such as a bandgap voltage that does not depend on the temperature, and a temperature dependent voltage TDV such as a threshold voltage Vt of a MOS transistor and amplifies a difference therebetween, thereby to change the period of the ring oscillator 1. In FIG. 1, (B) and (C) show structural examples for changing the period of the ring oscillator 1, wherein (B) shows the type of controlling the current supplied to the inverters, while (C) shows the type of changing an RC time constant of a load of each inverter. In these types, when temperature drops, the period for performing the refresh is automatically made longer so that the refresh current can be reduced.
In the conventional circuit examples shown in FIG. 1, the operational amplifier 3 requires an analog circuit such as a current mirror, and a DC current of about several tens of micro-amperes flows therethrough. In general, inasmuch as the temperature is constantly monitored, such a DC current constantly flows. As a result, even if the refresh current itself can be reduced, because of the increase of the current consumption following the operation of the circuit shown in FIG. 1, the total current in a data retention mode of the DRAM may not be lowered but increased contrariwise. Specifically, there arises a problem that even if the refresh current itself is reduced, if the circuit monitoring the temperature consumes much current, the total current required during the data retention mode of the DRAM is not lowered. This problem becomes particularly serious for battery-driven devices wherein all the current in the data retention mode of the DRAM is fed from a battery.
Further, the period range that can be controlled by the output voltage range of the operational amplifier 3 of FIG. 1 is limited. Specifically, the low temperature requires a period that is several times longer than the minimum period required at the high temperature, but it is difficult to change the period over such a wide range using the circuits shown in FIG. 1, so that ideal reduction of the refresh current at the low temperature is not made possible.